1. Field of the Invention
The present invention relates to a trench substrate and a method of manufacturing the same.
2. Description of the Related Art
Recently, in response to the densification of semiconductor chips and the increase in signal transmission rate, there is an increasing demand for a technology for the direct mounting of a semiconductor chip onto a printed circuit board. Accordingly, the development of a highly compact and reliable printed circuit board capable of accommodating the densification of semiconductor chips is being intensively required.
Requirements for such a highly compact and reliable printed circuit board are closely related to specifications of the semiconductor chips, and fulfillment of the requirements encounters numerous tasks such as realizing fine circuits, high electrical properties, structures enabling a high signal transmission rate, high reliability and high performance. To satisfy these requirements, a technology of creating fine circuit patterns and micro via-holes on printed circuit boards is of the utmost importance.
Typical processes of forming a circuit pattern on a printed circuit board may include a subtractive process, a full additive process, a semi-additive process and the like. Among these processes, the semi-additive process which is capable of achieving a fine circuit pattern is attracting many people's attention.
FIGS. 1 to 6 are cross-sectional views sequentially showing a conventional semi-additive process of forming a circuit pattern. The semi-additive process of forming a circuit pattern will now be described with reference to the drawings.
As shown in FIG. 1, a via-hole 16 is first formed in an insulating layer 12 which includes a metal layer 14 on one side thereof.
As shown in FIG. 2, an electroless plating layer 18 is formed on the insulating layer 2 and the internal surface of the via-hole 16 formed in the insulating layer 12. In this regard, the electroless plating layer 18 serves as a pretreatment layer for a subsequent electrolytic plating process, and must have or exceed a predetermined thickness (for example, 1 μm or more) in order to allow an electrolytic plating layer 24 to be formed thereon in the subsequent process.
As shown in FIG. 3, a dry film 20 is applied onto the electroless plating layer 18, and is then patterned to form openings 22 through which a region for formation of a circuit pattern is exposed.
As shown in FIG. 4, the electrolytic plating layer 24 is formed in both the via-hole 16 and the openings 22.
As shown in FIG. 5, the dry film 20 is removed.
Finally, as shown in FIG. 6, the region of the electroless plating layer 18 which is not covered with the electrolytic plating layer 24 is eliminated using flash etching, quick etching and the like, thus providing a circuit pattern 28 that includes a via 26.
However, since the circuit pattern 28, which is manufactured using the conventional semi-additive process, is configured into a raised structure on the insulating layer 12, the circuit pattern 28 is apt to separate from the insulating layer 12. In particular, in response to the recent trend of the circuit pattern 28 becoming fine, a bonding area between the insulating layer 12 and the circuit pattern 28 is decreased and thus adhesive force acting therebetween is decreased, resulting in the easy separation of the circuit pattern 28.
These days, new processes which are designed to overcome these limitations are proposed. Above all, an LPP (Laser Patterning Process) in which a trench is formed using laser machining and then a circuit pattern is formed through plating, polishing and etching processes is attracting many people's attention.
FIGS. 7 to 10 are cross-sectional views sequentially showing another conventional process of forming a circuit pattern through an LPP. The process of forming a circuit pattern will now be described with reference to the drawings.
As shown in FIG. 7, trenches 56 including a circuit pattern trench 56a and a via trench 56b are formed on an insulating layer 52 that includes a metal layer 54 layered on one side thereof.
As shown in FIG. 8, an electroless plating layer 58 is formed on both the internal surface of the trench 56 and the insulating layer 52.
As shown in FIG. 9, an electrolytic plating layer 60 is formed on the electroless plating layer 58.
Finally, as shown in FIG. 10, the upper portions of the electroless plating layer 58 and the electrolytic plating layer 60, which protrude from the insulating layer 52, are removed through etching and polishing processes, thus creating an embedded circuit pattern 64 that includes a via 62.
From FIG. 9, it will be appreciated that the electrolytic plating layer 60, which is formed in the trenches 56 and on the insulating layer 52, has a difference (plating deviation) between a height at the trench 56 and a height at a region other than the trench 56. For this reason, even though the upper portions of the electroless plating layer 58 and the electrolytic plating layer 60, which protrude from the insulating layer 52, are removed through an etching or polishing process, there is a limit to the fulfillment of an even surface regardless of regions.
In particular, because the portion of the electrolytic plating layer 60 which is positioned at a region other than the trench 56 protrudes upward from the insulating layer 52 more than the portion of electrolytic plating layer 60 which is positioned at the trench 56, the portion of the electrolytic plating layer 60 formed on the insulating layer 52 is not thoroughly removed, and thus adjacent lines of the circuit pattern 64 are not separated from each other. Meanwhile, when the electrolytic plating layer 60 is excessively removed, all the electrolytic plating layer 60 in the circuit pattern 64 and the via 62 are completely removed.